Conventional dynamic random access memory (DRAM) devices have widely been used in the main memory of personal computers. In a DRAM that is used as part of a main memory, read and write operations typically are performed with a burst length that is set based on internal register values in the DRAM and a data width that is fixed by a data mask signal DQM. Typically, the DRAM has a relatively large data width, such as, for example, x16 or x32.
FIG. 1 is a timing chart showing a data output scheme according to a conventional addressing method in a DRAM. A row address RA is input together with an active command ACTIVE in synchronization with a clock signal CLOCK. Then a column address, for example, xxxxxx00, is input together with a read command READ. Memory cell data corresponding to the row address and the column address are output to 1st through 16th data input/output (I/O) pads DQ0 through DQ15 in synchronization with the clock signal CLOCK after a predetermined time period. Data corresponding to a burst length of, for example, 4 (BL=4), i.e., memory cell data corresponding to column addresses xxxxxx00->xxxxxx01->xxxxxx10->xxxxxx11, are sequentially output to the 16 data I/O pads DQ0 through DQ15 in synchronization with the clock signal CLOCK.
When a DRAM having a data width of x16 is used in system applications that need a smaller data width such as x4 and x8 (e.g., notebook computers, mobile phones, or PDAs), the surplus data width may increase power consumption.